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general description the max1112/max1113 low-power, 8-bit, 8-channelanalog-to-digital converters (adcs) feature an internal track/hold, voltage reference, clock, and serial inter- face. they operate from a single 4.5v to 5.5v supply and consume only 135? while sampling at rates up to 50ksps. the max1112? 8 analog inputs and the max1113? 4 analog inputs are software-configurable, allowing unipolar/bipolar and single-ended/differential operation. successive-approximation conversions are performed using either the internal clock or an external serial-inter- face clock. the full-scale analog input range is deter- mined by the 4.096v internal reference, or by an externally applied reference ranging from 1v to v dd . the 4-wire serial interface is compatible with the spi,qspi, and microwire serial-interface standards. a serial-strobe output provides the end-of-conversion signal for interrupt-driven processors. the max1112/max1113 have a software-program- mable, 2? automatic power-down mode to minimize power consumption. using power-down, the supply current is reduced to 13? at 1ksps, and only 82? at 10ksps. power-down can also be controlled using the shdn input pin. accessing the serial interface automat- ically powers up the device.the max1112 is available in a 20-pin ssop package. the max1113 is available in a small 16-pin qsop package. ________________________applications portable data logginghand-held measurement devices medical instruments system diagnostics solar-powered remote systems 4ma to 20ma-powered remote data-acquisition systems ____________________________features ? 4.5v to 5.5v single supply ? low power: 135a at 50ksps 13a at 1ksps ? 8-channel single-ended or 4-channel differentialinputs (max1112) ? 4-channel single-ended or 2-channel differentialinputs (max1113) ? internal track/hold; 50khz sampling rate ? internal 4.096v reference ? spi/qspi/microwire-compatible serial interface ? software-configurable unipolar or bipolar inputs ? total unadjusted error: 1 lsb (max) 0.3 lsb (typ) max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs ________________________________________________________________ maxim integrated products 1 input shift register control logic int clock output shift register +4.096v reference t/h analog input mux 8-bit sar adc in doutsstrb v dd dgndagnd sclk din ch0ch1 ch3 ch2 ch7* ch6* ch5* ch4* com refout *max1112 only refin out ref clock max1112max1113 cs shdn functional diagram 19-1231; rev 2; 4/11 evaluation kit available ordering information continued at end of data sheet. pin configurations appear at end of data sheet. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to agnd............................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v ch0?h7, com, refin, refout to agnd ...................................-0.3v to (v dd + 0.3v) digital inputs to dgnd.............................................-0.3v to +6v digital outputs to dgnd ............................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70?) qsop (derate 8.30mw/? above +70?) .....................667mw ssop (derate 8.00mw/? above +70?) .....................640mw operating temperature ranges max1112cap/max1113cee...............................0? to +70? max1112eap/max1113eee ............................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? electrical characteristics(v dd = 4.5v to 5.5v; unipolar input mode; v com = 0v; f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1? capacitor at refout; t a = t min to t max ; unless otherwise noted.) -3db rolloff mhz 1.5 small-signal bandwidth khz 800 v ch_ = 4.096v p-p , 25khz (note 3) external reference, 4.096v no missing codes over temperature conditions full-power bandwidth ? internal or external reference lsb gain error (note 2) db -75 channel-to-channel crosstalk db 68 sfdr spurious-free dynamic range db -70 thd total harmonic distortion (up to the 5th harmonic) lsb ?.1 channel-to-channel offset matching ppm/? ?.8 gain temperature coefficient lsb ? dnl differential nonlinearity units min typ max symbol parameter lsb ?.3 ? tue total unadjusted error bits 8 resolution db 49 sinad signal-to-noise and distortion ratio lsb ?.1 ?.5 inl relative accuracy (note 1) lsb ?.3 ? offset error dc accuracy dynamic specifications (10.034khz sine-wave input, 4.096v p-p , 50ksps, 500khz external clock) downloaded from: http:///
? max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs _______________________________________________________________________________________ 3 electrical characteristics (continued)(v dd = 4.5v to 5.5v; unipolar input mode; v com = 0v; f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1? capacitor at refout; t a = t min to t max ; unless otherwise noted.) on/off leakage current, v ch_ = 0v or v dd used for data transfer only (note 5) external clock, 2mhz conditions ppm/? ?0 ma 6 refout short-circuit current pf 18 input capacitance ? ?.01 ? multiplexer leakage current 1 2 50 500 khz 400 internal clock frequency 0 to 0.5ma output load mv 4.5 load regulation (note 7) ns 10 aperture delay ? 1 t acq track/hold acquisition time units min typ max symbol parameter ps v 1 v dd + 50 input voltage range (note 8) ? 12 0 input current < 50 aperture jitter external clock, 500khz, 10 clocks/conversion 20 internal clock ? 25 55 t conv conversion time (note 4) bipolar input, v com = v refin /2 unipolar input, v com = 0v com v refin /2 v 0v refin input voltage range, single-ended and differential (note 6) v 3.936 4.096 4.256 refout voltage external clock-frequency range mhz khz capacitive bypass at refout ? refout temperature coefficient v 4.5 5.5 v dd supply voltage v dd = 4.5v to 5.5v; external reference, 4.096v; full-scale input mv ?.4 ? psr power-supply rejection (note 9) 2 power-down 3.2 10 software shdn at dgnd operating mode 135 250 full-scale inputc load = 10pf reference disabled 95 i dd ? supply current conversion rate analog input internal reference external reference at refin power requirements downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 4 _______________________________________________________________________________________ electrical characteristics (continued)(v dd = 4.5v to 5.5v; unipolar input mode; v com = 0v; f sclk = 500khz, external clock (50% duty cycle); 10 clocks/conversion cycle (50ksps); 1? capacitor at refout; t a = t min to t max ; unless otherwise noted.) cs = v dd (note 5) cs = v dd i source = 0.5ma i sink = 5ma shdn = open shdn = 0v or v dd (note 5) digital inputs = 0v or v dd v shdn = open conditions pf 15 c out three-state output capacitance ? ?.01 ?0 i l three-state leakage current v v dd - 0.5 v oh output high voltage v 0.4 v ol output low voltage na ?00 shdn maximum allowed leakage for mid-input v v dd /2 v flt shdn voltage, high impedance ? ? shdn input current v v dd - 0.4 v sh shdn input high voltage v 0.8 v il din, sclk, cs input low voltage v 1.1 v dd - 1.1 i sink = 16ma v sm 0.8 pf 15 c in din, sclk, cs input capacitance ? ? i in din, sclk, cs input leakage shdn input mid-voltage v 0.2 v hyst din, sclk, cs input hysteresis units min typ max symbol parameter v 0.4 v sl shdn input low voltage v v ih din, sclk, cs input high voltage 3 digital inputs (din, sclk, cs) digital outputs (dout, sstrb) shdn input downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs _______________________________________________________________________________________ 5 ns 100 t css figure 1, external clock mode only, c load = 100pf ns cs to sclk rise setup 240 figure 1, c load = 100pf ns 20 200 ns 0 t csh conditions cs to sclk rise hold 240 t dv cs fall to output enable figure 2, c load = 100pf ns 240 t tr cs rise to output disable t sdv cs fall to sstrb output enable (note 5) figure 2, external clock mode only, c load = 100pf ns 240 t str cs rise to sstrb output disable (note 5) figure 11, internal clock mode only ns 0 t sck sstrb rise to sclk rise (note 5) ns 200 t ch sclk pulse width high ns 200 t cl sclk pulse width low c load = 100pf ns 240 t sstrb sclk fall to sstrb ns 0 t dh din to sclk hold ? 1 t acq track/hold acquisition time ns 100 t ds din to sclk setup units min typ max symbol parameter timing characteristics (figures 8 and 9) (v dd = 4.5v to 5.5v, t a = t min to t max , unless otherwise noted.) note 1: relative accuracy is the analog value? deviation (at any code) from its theoretical value after the full-scale range is calibrated. note 2: v refin = 4.096v, offset nulled. note 3: on-channel grounded; sine wave applied to all off-channels. note 4: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 5: guaranteed by design. not subject to production testing. note 6: common-mode range for the analog inputs is from agnd to v dd . note 7: external load should not change during the conversion for specified accuracy. note 8: external reference at 4.096v, full-scale input, 500khz external clock. note 9: measured as | v fs (4.5v) - v fs (5.5v) | . note 10: 1? at refout; internal reference settling to 0.5 lsb. ns t do sclk fall to output data valid figure 1, c load = 100pf external reference 20 internal reference (note 10) ? 24 t wake wakeup time ms downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 6 _______________________________________________________________________________________ __________________________________________typical operating characteristics (v dd = 5.0v; f sclk = 500khz; external clock (50% duty cycle); r l = ; t a = +25?, unless otherwise noted.) 180100 -60 140 supply current vs. temperature 120 max1112/13-01 temperature (c) supply current ( a) -20 20 60 100 160140 output code = full scalec load = 10pf v dd = 5.5v v dd = 4.5v 10 0 -60 140 shutdown supply current vs. temperature 2 8 max1112/13-02 temperature (c) shutdown supply current ( a) -20 20 60 100 64 shdn = dgnd 0.3 -0.3 02 5 6 differential nonlinearity vs. code -0.2 0.20.1 max1112/13-03 digital code dnl (lsb) 64 128 192 0 -0.1 0.6 0 -60 140 offset error vs. temperature 0.1 0.2 0.5 max1112/13-04 temperature (c) offset error (lsb) -20 20 60 100 0.40.3 0.20 -0.20 02 5 6 integral nonlinearity vs. code -0.10-0.15 0.150.10 0.05 max1112/13-05 digital code inl (lsb) 64 128 192 0 -0.05 20 -100 02 5 fft plot -80 -20 0 max1112/13-06 frequency (khz) amplitude (db) 5 1 01 52 0 -60 -40 f ch_ = 10.034khz, 4v p-p f sample = 50ksps downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs _______________________________________________________________________________________ 7 pin description 16 sstrb serial-strobe output. in internal clock mode, sstrb goes low when the max1112/max1113 begin the a/d conversion and goes high when the conversion is complete. in external clock mode, sstrb pulses high for two clock periods before the msb is shifted out. high impedance when cs is high (external clock mode only). 20 v dd positive supply voltage, 4.5v to 5.5v. bypass to agnd with 0.1? and 1? capacitoras close as possible to the device. place the 0.1? capacitor closer to v p-p . 18 cs active-low chip select. data is not clocked into din unless cs is low. when cs is high, dout is high impedance. 19 sclk serial-clock input. clocks data in and out of serial interface. in external clock mode,sclk also sets the conversion speed (duty cycle must be 45% to 55%). 17 din serial-data input. data is clocked in at sclk? rising edge. 12 refout internal reference generator output. bypass with a 1? capacitor to agnd. 14 dgnd digital ground 15 dout serial-data output. data is clocked out on sclk? falling edge. high impedance whencs is high. 13 agnd analog ground 10 shdn three-level shutdown input. normally high impedance. pulling shdn low shuts the max1112/max1113 down to 10? (max) supply current; otherwise, the devices arefully operational. pulling shdn high shuts down the internal reference. 11 refin reference voltage input for analog-to-digital conversion. connect to refout to usethe internal reference. 5? ch4?h7 sampling analog inputs 1? ch0?h3 sampling analog inputs +5v 3k c load dgnd dout c load dgnd 3k dout a) high-z to v oh and v ol to v oh b) high-z to v ol and v oh to v ol figure 1. load circuits for enable time +5v 3k c load dgnd dout c load dgnd 3k dout a) v oh to high-z b) v ol to high-z figure 2. load circuits for disable time 12 16 14 15 13 8 10 11 9 6 7 1? 5 9 com ground reference for analog inputs. sets zero-code voltage in single-ended mode.must be stable to ?.5 lsb. pin max1113 name function max1112 downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 8 _______________________________________________________________________________________ _______________detailed description the max1112/max1113 analog-to-digital converters(adcs) use a successive-approximation conversion technique and input track/hold (t/h) circuitry to convert an analog signal to an 8-bit digital output. a flexible seri- al interface provides easy interface to microprocessors (?s). figure 3 shows the typical operating circuit. pseudo-differential input the sampling architecture of the adc? analog com-parator is illustrated in figure 4, the equivalent input cir- cuit. in single-ended mode, in+ is internally switched to the selected input channel, ch_, and in- is switched to com. in differential mode, in+ and in- are selected from the following pairs: ch0/ch1, ch2/ch3, ch4/ch5, and ch6/ch7. configure the max1112 channels with table 1 and the max1113 channels with table 2. in differential mode, in- and in+ are internally switched to either of the analog inputs. this configuration is pseudo-differential to the effect that only the signal at in+ is sampled. the return side (in-) must remain sta- ble within ?.5 lsb (?.1 lsb for best results) with respect to agnd during a conversion. to accomplish this, connect a 0.1? capacitor from in- (the selected analog input) to agnd if necessary. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans two sclk cycles and endson the falling sclk edge after the last bit of the input control word has been entered. at the end of the acqui- sition interval, the t/h switch opens, retaining charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplex-er switching c hold from the positive input (in+) to the negative input (in-). in single-ended mode, in- is sim-ply com. this unbalances node zero at the input of the comparator. the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 8-bit resolution. this action is equivalent to transferring a charge of 18pf x (v in+ - v in- ) from c hold to the binary-weighted capac- itive dac, which in turn forms a digital representation ofthe analog input signal. track/hold the t/h enters its tracking mode on the falling clockedge after the sixth bit of the 8-bit control byte has been shifted in. it enters its hold mode on the falling clock edge after the eighth bit of the control byte has been shifted in. if the converter is set up for single- ended inputs, in- is connected to com, and the con- verter samples the ??input; if it is set up for differential inputs, in- connects to the ??input, and the difference (in+ - in-) is sampled. at the end of the conversion, the positive input connects back to in+, and c hold charges to the input signal. v dd i/o sck (sk)mosi (so) miso (si) v ss shdn sstrb dout din sclk cs com dgnd agnd v dd ch7 1 f 0.1 f 1 f ch0 analog inputs max1112max1113 cpu +5v refin refout figure 3. typical operating circuit ch0 ch1 ch2ch3 ch4*ch5* ch6* ch7* com c switch track t/h switch c hold hold capacitive dac refin zero comparator ? + 18pf 6.5k r in single-ended mode: in+ = cho?ch7, in- = com.differential mode: in+ and in- selected from pairs of ch0/ch1, ch2/ch3, ch4*/ch5*, ch6*/ch7*. *max1112 only at the sampling instant,the mux input switches from the selected in+ channel to the selected in- channel. input mux figure 4. equivalent input circuit downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs _______________________________________________________________________________________ 9 table 1a. max1112 channel selection in single-ended mode (sgl/ dif = 1) table 1b. max1112 channel selection in differential mode (sgl/ dif = 0) table 2a. max1113 channel selection in single-ended mode (sgl/ dif = 1) table 2b. max1113 channel selection in differential mode (sgl/ dif = 0) + 1 1 1 + 1 ch2 1 0 + 0 ch3 1 1 + 0 ch1 1 0 + 1 + ch0 0 1 + 1 0 0 + 0 0 1 com ch7 ch6 sel2 ch5 ch4 0 0 0 sel0 sel1 + 1 1 1 + 0 ch2 1 1 + 1 ch3 0 1 + 0 ch1 0 1 + 1 + ch0 1 0 + 0 1 0 + 1 0 0 ch7 ch6 sel2 ch5 ch4 0 0 0 sel0 sel1 + x 1 1 + x ch1 1 0 + ch0 + x 0 1 sel2 ch3 ch2 x 0 0 sel0 sel1 + x 1 1 + x ch1 0 1 + ch0 + x 1 0 sel2 ch3 ch2 x 0 0 sel0 sel1 com downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 10 ______________________________________________________________________________________ table 3. control-byte format start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) name sgl/ dif 2 bit 1 = single ended, 0 = differential. selects single-ended or differential conversions. in single- ended mode, input signal voltages are referred to com. in differential mode, the voltage differ-ence between two channels is measured (tables 1 and 2). description uni/ bip 3 start 1 = unipolar, 0 = bipolar. selects unipolar or bipolar conversion mode (table 4). pd0 0 (lsb) 7 (msb) 1 = external clock mode, 0 = internal clock mode. selects external or internal clock mode. the first logic 1 ?bit after cs goes low defines the beginning of the control byte. sel2sel1 sel0 65 4 select which of the input channels are to be used for the conversion (tables 1 and 2). pd1 1 1 = fully operational, 0 = power-down. selects fully operational or power-down mode. the time required for the t/h to acquire an input signalis a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. the acquisition time, t acq , is the minimum time needed for the signal to be acquired. it is calculated by: t acq = 6 x (r s + r in ) x 18pf where r in = 6.5k , r s = the source impedance of the input signal, and t acq is never less than 1?. note that source impedances below 2.4k do not significantly affect the ac performance of the adc. input bandwidth the adc? input tracking circuitry has a 1.5mhz small-signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid high- frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog inputs internal protection diodes, which clamp the analoginput to v dd and agnd, allow the channel input pins to swing from (agnd - 0.3v) to (v dd + 0.3v) without dam- age. however, for accurate conversions near full scale,the inputs must not exceed v dd by more than 50mv or be lower than agnd by 50mv.if the analog input exceeds 50mv beyond the sup- plies, do not forward bias the protection diodes of off channels over 2ma. the max1112/max1113 can be configured for differen- tial or single-ended inputs with bits 2 and 3 of the con- trol byte (table 3). in single-ended mode, analog inputs are internally referenced to com with a full-scale input range from com to v refin + com. for bipolar opera- tion, set com to v refin /2. in differential mode, choosing unipolar mode sets thedifferential input range at 0v to v refin . in unipolar mode, the output code is invalid (code zero) when anegative differential input voltage is applied. bipolar mode sets the differential input range to ? refin /2. note that in this mode, the common-mode input rangeincludes both supply rails. see table 4 for input voltage ranges. quick look to quickly evaluate the max1112/max1113? analogperformance, use the circuit of figure 5. the max1112/max1113 require a control byte to be written to din before each conversion. tying din to +5v feeds downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs ______________________________________________________________________________________ 11 in control bytes of $ff (hex), which trigger single-ended, unipolar conversions on ch7 (max1112) or ch3 (max1113) in external clock mode without power- ing down between conversions. in external clock mode, the sstrb output pulses high for two clock periods before the most significant bit (msb) of the 8-bit con- version result is shifted out of dout. varying the ana- log input alters the output code. a total of 10 clock cycles is required per conversion. all transitions of the sstrb and dout outputs occur on sclk? falling edge. how to start a conversion a conversion is started by clocking a control byte intodin. with cs low, each rising edge on sclk clocks a bit from din into the max1112/max1113? internal shift reg-ister. after cs falls, the first arriving logic ??bit at din defines the msb of the control byte. until this first start bitarrives, any number of logic ??bits can be clocked into din with no effect. table 3 shows the control-byte format. the max1112/max1113 are compatible with microwire, spi, and qspi devices. for spi, select the correct clock polarity and sampling edge in the spi con- trol registers: set cpol = 0 and cpha = 0. microwire, spi, and qspi all transmit a byte and receive a byte at the same time. using the typical operating circuit (figure 3), the simplest software interface requires three 8-bit trans- fers to perform a conversion (one 8-bit transfer to config- ure the adc, and two more 8-bit transfers to clock out the 1f 0.1f v dd dgnd agnd cs sclk din dout sstrb shdn +5v n.c. 0.01f ch7 (ch3) com refout refin c11f 0v to +4.096v analog input oscilloscope ch1 ch2 ch3 ch4 *full-scale analog input, conversion result = $ff (hex) ( ) are for the max1113. max1112max1113 +5v 500khz oscillator sclk sstrb dout* figure 5. quick-look circuit table 4. full-scale and zero-scale voltages unipolar mode v refin + com +v refin /2 + com full scale com com -v refin /2 + com positive full scale zero scale zero scale bipolar mode negative full scale downloaded from: http:///
8-bit conversion result). figure 6 shows the max1112/max1113 common serial-interface connections. simple software interface make sure the cpu? serial interface runs in mastermode so the cpu generates the serial clock. choose a clock frequency from 50khz to 500khz. 1) set up the control byte for external clock mode and call it tb1. tb1 should be of the format 1xxxxx11binary, where the xs denote the particular channel and conversion mode selected. 2) use a general-purpose i/o line on the cpu to pull cs low. 3) transmit tb1 and, simultaneously, receive a byte and call it rb1. ignore rb1. 4) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb2. 5) transmit a byte of all zeros ($00 hex) and, simulta- neously, receive byte rb3. 6) pull cs high. figure 7 shows the timing for this sequence. bytes rb2and rb3 contain the result of the conversion padded with two leading zeros and six trailing zeros. the total conversion time is a function of the serial-clock frequency and the amount of idle time between 8-bit transfers. make sure that the total conversion time does not exceed 1ms, to avoid excessive t/h droop. max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 12 ______________________________________________________________________________________ sstrb cs sclk din dout 14 8 1 2 1 6 2 0 2 4 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b7 b6 b5 b4 b3 b2 b1 b0 acquisition (f sclk = 500khz) idle filled with zeros idle conversion t acq a/d state rb1 rb2 rb3 4 s figure 7. single-conversion timing, external clock mode, 24 clocks cs sclk dout i/o sck miso +5v ss a) spi cssclk dout cs sck miso +5v ss b) qspi max1112max1113 max1112max1113 max1112max1113 cssclk dout i/o sk si c) microwire figure 6. common serial-interface connections to themax1112/max1113 downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs ______________________________________________________________________________________ 13 digital output in unipolar input mode, the output is straight binary(figure 15). for bipolar inputs, the output is two?-com- plement (figure 16). data is clocked out at sclk? falling edge in msb-first format. clock modes the max1112/max1113 can use either an external ser-ial clock or the internal clock to perform the successive- approximation conversion. in both clock modes, the external clock shifts data in and out of the devices. bit pd0 of the control byte programs the clock mode. figures 8?1 show the timing characteristics common to both modes. external clock in external clock mode, the external clock not onlyshifts data in and out, it also drives the analog-to-digital conversion steps. sstrb pulses high for two clockperiods after the last bit of the control byte. successive- approximation bit decisions are made and appear at dout on each of the next eight sclk falling edges (figure 7). after the eight data bits are clocked out, subsequent clock pulses clock out zeros from the dout pin. sstrb and dout go into a high-impedance state when cs goes high; after the next cs falling edge, sstrb outputs a logic low. figure 9 shows the sstrbtiming in external clock mode. the conversion must complete in 1ms, or droop on the sample-and-hold capacitors can degrade conversion results. use internal clock mode if the serial-clock fre- quency is less than 50khz, or if serial-clock interruptions could cause the conversion interval to exceed 1ms. ? ? ?? ? ? ? ? ? ? ? ? cs sclk din dout t css t cl t ds t dh t dv t do t ch t do t tr t csh figure 8. detailed serial-interface timing ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? t sdv t sstrb pd0 clocked in t str sstrb sclk cs t sstrb ? ? ? ? figure 9. external clock mode sstrb detailed timing downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 14 ______________________________________________________________________________________ sstrb cs sclk din dout 14 8 12 15 17 start sel2 sel1 sel0 uni/ bip sgl/ dif pd1 pd0 b7 b6 b1 b0 t acq 4s (f sclk = 500khz) idle filled with zeros idle conversion 25s typ a/d state 2 3 5 6 7 9 10 11 16 18 t conv figure 10. internal clock mode timing pd0 clock in t sstrb t csh t conv t sck sstrb sclk t css note: for best noise performance, keep sclk low during conversion. cs figure 11. internal clock mode sstrb detailed timing internal clock internal clock mode frees the ? from the burden ofrunning the sar conversion clock. this allows the con- version results to be read back at the processor? con- venience, at any clock rate up to 2mhz. sstrb goes low at the start of the conversion and then goes high when the conversion is complete. sstrb is low for 25? (typ), during which time sclk should remain low for best noise performance. an internal register stores data when the conversion is in progress. sclk clocks the data out of this register at any time after the conversion is complete. after sstrb goes high, the second falling clock edge produces the msb of the conversion at dout, followed by the remaining bits in msb-first format (figure 10). cs does not need to be held low once a conversion is started.pulling cs high prevents data from being clocked into the max1112/max1113 and three-states dout, but itdoes not adversely affect an internal clock-mode con- version already in progress. when internal clock mode is selected, sstrb does not go into a high-impedance state when cs goes high. figure 11 shows the sstrb timing in internal clockmode. in this mode, data can be shifted in and out of the max1112/max1113 at clock rates up to 2mhz, pro- vided that the minimum acquisition time, t acq , is kept above 1?. downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs ______________________________________________________________________________________ 15 sclk din dout cs s control byte 0 control byte 1 s conversion result 0 b7 b0 b7 b0 b7 conversion result 1 conversion result 2 sstrb control byte 2 s 1 888 10 1 10 1 10 1 control byte 3 s figure 12a. continuous conversions, external clock mode, 10 clocks/conversion timing cs sclk din dout s control byte 0 control byte 1 s conversion result 0 b7 b0 b7 conversion result 1 figure 12b. continuous conversions, external clock mode, 16 clocks/conversion timing data framing the falling edge of cs does not start a conversion. the first logic high clocked into din is interpreted as a startbit and defines the first bit of the control byte. a conver- sion starts on the falling edge of sclk, after the eighth bit of the control byte (the pd0 bit) is clocked into din. the start bit is defined as: the first high bit clocked into din with cs low any time the converter is idle, e.g., after v dd is applied. or the first high bit clocked into din after the msb of aconversion in progress is clocked onto the dout pin. if cs is toggled before the current conversion is com- plete, then the next high bit clocked into din is recog-nized as a start bit; the current conversion is terminated, and a new one is started. the fastest the max1112/max1113 can run is 10 clocks per conversion. figure 12a shows the serial- interface timing necessary to perform a conversion every 10 sclk cycles in external clock mode. many microcontrollers require that conversions occur in multiples of eight sclk clocks; 16 clocks per conver- sion is typically the fastest that a microcontroller can drive the max1112/max1113. figure 12b shows the serial-interface timing necessary to perform a conver- sion every 16 sclk cycles in external clock mode. downloaded from: http:///
__________applications information power-on reset when power is first applied, and if shdn is not pulled low, internal power-on reset circuitry activates themax1112/max1113 in internal clock mode. sstrb is high on power-up and, if cs is low, the first logical 1 on din is interpreted as a start bit. until a conversion takesplace, dout shifts out zeros. no conversions should be performed until the reference voltage has stabilized (see the wakeup time specifications in the timing characteristics ). power-down when operating at speeds below the maximum sam-pling rate, the max1112/max1113? automatic power- down mode can save considerable power by placing the converters in a low-current shutdown state between conversions. figure 13 shows the average supply cur- rent as a function of the sampling rate. select power-down with pd1 of the din control byte with shdn high or high impedance (table 3). pull shdn low at any time to shut down the converters com- pletely. shdn overrides pd1 of the control byte. figures 14a and 14b illustrate the various power-downsequences in both external and internal clock modes. software power-down software power-down is activated using bit pd1 of thecontrol byte. when software power-down is asserted, the adcs continue to operate in the last specified clock mode until the conversion is complete. the adcs then power down into a low quiescent-current state. in internal clock mode, the interface remains active, and conversion results can be clocked out after the max1112/ max1113 have entered a software power-down. the first logical 1 on din is interpreted as a start bit, which powers up the max1112/max1113. if the din byte contains pd1 = 1, then the chip remains powered up. if pd1 = 0, power-down resumes after one conversion. hard-wired power-down pulling shdn low places the converters in hard-wired power-down. unlike software power-down, the conversionis not completed; it stops coincidentally with shdn being brought low. shdn also controls the state of the internal reference (table 5). letting shdn high impedance enables the internal 4.096v voltage reference. whenreturning to normal operation with shdn high impedance, there is a t rc delay of approximately 1m x c load , where c load is the capacitive loading on the shdn pin. pulling shdn high disables the internal reference, which saves power when using an external reference. external reference an external reference between 1v and v dd should be connected directly at the refin terminal. the dc inputimpedance at refin is extremely high, consisting of leakage current only (typically 10na). during a conver- sion, the reference must be able to deliver up to 20? average load current and have an output impedance of 1k or less at the conversion clock frequency. if the reference has higher output impedance or is noisy,bypass it close to the refin pin with a 0.1? capacitor. if an external reference is used with the max1112/ max1113, connect shdn to v dd to disable the internal reference and decrease power consumption. max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 16 ______________________________________________________________________________________ table 5. hard-wired power-down andinternal reference state shdn state device mode 1 enabled high impedance enabled 0 power-down internal reference disabled disabled enabled 1000 10 01 0 3 0 5 0 100 max1112/13-fig13 sampling rate (ksps) supply current ( a) 20 40 v dd = v refin = 5v c load at dout + sstrb c load = 30pf code = 11111111 c load = 30pf code = 10101010 c load = 60pf code = 10101010 figure 13. average supply current vs. sampling rate downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs ______________________________________________________________________________________ 17 internal reference to use the max1112/max1113 with the internal refer-ence, connect refin to refout. the full-scale range of the max1112/max1113 with the internal reference is typically 4.096v with unipolar inputs, and ?.048v with bipolar inputs. the internal reference should be bypassed to agnd with a 1? capacitor placed as close to the refin pin as possible. transfer function table 4 shows the full-scale voltage ranges for unipolarand bipolar modes. figure 15 depicts the nominal, unipolar i/o transfer function, and figure 16 shows the bipolar i/o transfer function when using a 4.096v refer- ence. code transitions occur at integer lsb values. output coding is binary, with 1 lsb = 16mv (4.096v/256) for unipolar operation and 1 lsb = 16mv [(4.096v/2 - -4.096v/2)/256] for bipolar operation. powered up power- down powered up powered up data valid data valid data invalid external external internal sx xxxx 11 s 01 xx xx x xx xxx s1 1 power- down mode dout din clock mode shdn sets externalclock mode sets external clock mode sets power-down mode figure 14a. power-down modes, external clock timing diagram power-down powered up powered up data valid data valid internal clock mode sx xxxx 10 s 00 xx xxx s mode dout din sets internalclock mode sets power-down mode conversion conversion sstrb figure 14b. power-down modes, internal clock timing diagram downloaded from: http:///
layout, grounding, and bypassing for best performance, use printed circuit boards. wire-wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 17 shows the recommended system ground connections. a single-point analog ground (star ground point) should be established at agnd, separate from the logic ground. connect all other analog grounds and dgnd to the star ground. no other digital system ground should be connected to this ground. the ground return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply can affect the comparator in the adc. bypass the supply tothe star ground with 0.1? and 1? capacitors close to the v dd pin of the max1112/max1113. minimize capacitor lead lengths for best supply-noise rejection. ifthe 5v power supply is very noisy, a 10 resistor can be connected to form a lowpass filter. max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs 18 ______________________________________________________________________________________ +5v gnd supplies dgnd +5v dgnd agnd v dd digital circuitry max1112max1113 r* = 10 *optional figure 17. power-supply grounding connections 01111111 output code 0111111000000010 00000001 00000000 11111111 11111110 11111101 10000001 10000000 -fs com input voltage (lsb) +fs - 1 lsb 2 +fs = v refin + com 2 -fs = -v refin + com 2 com = v refin 2 1 lsb = v refin 256 figure 16. bipolar transfer function output code full-scale transition 1111111111111110 11111101 0000001100000010 00000001 00000000 123 0 fs fs - 1 lsb input voltage (lsb) (com) fs = v refin + com v refin 256 1 lsb = figure 15. unipolar transfer function downloaded from: http:///
max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs ______________________________________________________________________________________ 19 2019 18 17 16 15 14 13 12 3 4 5 6 7 8 v dd sclk cs din ch3 ch2 ch1 ch0 top view sstrbdout dgnd agnd ch7 ch6 ch5 ch4 12 11 9 10 refoutrefin shdn com max1112 ssop 1615 14 13 12 11 10 9 12 3 4 5 6 7 8 v dd sclkcs din sstrb dout dgnd agnd ch0ch1 ch2 ch3 com shdn refin refout max1113 qsop pin configurations ___________________chip information ordering information part max1112c/d max1112eap+ -40? to +85? 0? to +70? temp range pin-package dice* 20 ssop process:cmossubstrate connected to dgnd max1112 cap+ 0? to +70? 20 ssop max1113 cee+ 0? to +70? 16 qsop max1113eee+ 40? to +85? 16 qsop + denotes a lead(pb)-free/rohs-compliant package. * dice are specified at t a = +25c, dc parameters only. package information for the latest package outline information and land patterns(footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 20 ssop a20+1 21-0056 90-0094 16 qsop e16+1 21-0055 90-0167 downloaded from: http:///
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. max1112/max1113 +5v, low-power, multi-channel, serial 8-bit adcs revision history revision number revision date description pages changed 0 6/97 initial release 2 4/11 updated general description , features , ordering information , absolute maximum ratings , electrical characteristics , timing characteristics , pin description , tables 3 and 4, 5, power-down , software power-down , hard- wired power-down , external reference and layout, grounding, and bypassing , and chip information sections. 1-8, 10, 11, 13, 14, 16, 18, 19 downloaded from: http:///

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